Hardware logic emulation (or acceleration) systems can be applied to implement a user design via one or more programmable integrated circuits. Such hardware logic emulation systems are commercially available from various vendors, such as Cadence Design Systems, Inc., headquartered in San Jose, Calif.
Typical hardware emulation systems utilize programmable logic devices (or integrated circuit chips) and/or processing devices (or integrated circuit chips) that are programmably interconnected. In programmable logic device-based emulation systems, for example, the logic comprising the user design can be programmed into at least one programmable logic device, such as field programmable gate array (FPGA). The logic embodied in the user design thereby can be implemented, taking an actual operating form, in the programmable logic device. Examples of conventional hardware logic emulation systems using programmable logic devices are disclosed in U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191, the respective disclosures of which are hereby incorporated herein by reference in their entireties.
Similarly, the user design can be processed in a processor-based emulation system so that its functionality appears to be created in the processing devices by calculating the outputs of the user design. The logic embodied in the user design thereby is not itself implemented in processor-based emulation systems. In other words, the logic embodied in the user design does not take an actual operating form in the processing systems. Illustrative conventional hardware logic emulation systems that use processing devices are disclosed in U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030, the respective disclosures of which are hereby incorporated herein by reference in their entireties.
One primary use for hardware logic emulation systems is debugging user designs. Thereby, any functional errors present in the user designs can be identified and resolved prior to fabrication of the user designs in actual silicon. Circuit designers have used hardware emulation systems for many years to perform such debugging because the alternatives, such as simulation, typically are much slower than emulation. Simulation is a software based approach; whereas, for emulation, the user design is compiled with a testbench to form a machine-executable model. Typically, the testbench is represented as a target system (or board) that can directly interact with the user design. The machine-executable model, once compiled, can be executed via a workstation or personal computer.
To facilitate compiling the machine-executable model, the user design usually is provided in the form of a netlist description. The netlist description describes the components of the user design and the electrical interconnections among the components. The components include each circuit element for implementing the user design. Exemplary conventional circuit elements are combinational logic circuit elements (or gates), sequential logic circuit elements, such as flip-flops and latches, and memory elements, such as static random access memory (SRAM) and dynamic random access memory (DRAM). Memory elements that are incorporated into the user design often are referred to as being “design memory systems.” The netlist description can be derived from any conventional source, such as a hardware description language, and is compiled to place the netlist description in a form that can be used by the emulation system.
Each design memory system of the user design is mapped onto a physical emulator memory system of the hardware emulation system during compilation. The emulator memory system typically has a fixed data width. For example, Cadence Design Systems, Inc., of San Jose, Calif., provides a Palladium II accelerator/emulation system with an emulator memory system that includes static random access memory (SRAM) and dynamic random access memory (DRAM). The static random access memory (SRAM) has a fixed data width of 32 data bits; whereas, the data width of the dynamic random access memory (DRAM) is 64 data bits.
For many memory-rich user designs, the emulator memory system therefore can quickly become a critical system resource. Each design memory system typically is mapped onto the emulator memory system without regard to the data width of the individual design memory systems. Therefore, even design memory systems with very small data widths, such as data widths of 1, 2, or 3 data bits, are mapped onto the fixed data width of the emulator memory system. As a result, a significant portion of many memory words in the emulator memory system can be “lost,” remaining unused during subsequent emulation. Such inefficient mapping from the design memory systems to the emulator memory system thereby results in a wasteful use of the critical system resource.
Prior attempts to provide more compact mapping between design memory systems and emulator memory systems have provided to be unsatisfactory. In one approach, different design memory systems are mapped onto the same address area of the emulation memory system. This approach, however, is difficult to implement and is not consistently effective. Others have suggested the use of manual methods for mapping the design memory systems onto the emulator memory system. In addition to being extremely difficult to apply to practical user designs, these manual methods have proven to be time consuming and prone to error.
In view of the foregoing, a need exists for an improved system and method for mapping between dissimilar memory systems that overcomes the aforementioned obstacles and deficiencies of currently-available memory mapping systems.
It should be noted that the figures are not drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the preferred embodiments of the present invention. The figures do not describe every aspect of the present invention and do not limit the scope of the invention.